Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be configured to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable tiles. These configurable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth. Notably, as used herein, the terms “include” or “including” mean include or including without limitation.
Each configurable tile typically includes both configurable interconnect and configurable logic. The configurable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by interconnect points. The configurable logic implements the logic of a user design using configurable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The configurable interconnect and configurable logic are typically configured by loading a stream of configuration data into internal configuration memory cells (for example, volatile or non-volatile memory cells) that define how the configurable elements are configured. For example, in the case of a CLB, for one set of configuration data a first logic circuit is formed and for a second set of configuration data a second logic circuit is formed. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FIG. 1 is a simplified illustration of an exemplary FPGA. The FPGA of FIG. 1 includes an array of programmable logic blocks (“LBs”) 11a through 11i and input/output circuit elements (“I/Os”) 12a through 12d. The LBs and I/O sections are interconnected by a programmable interconnect structure that includes a large number of interconnect lines 13 interconnected by programmable interconnect points (“PIPs”) 14, which are shown as small circles in FIG. 1. PIPs 14 are often coupled into groups, such as group 15, that implement multiplexer circuits selecting one of several interconnect lines to provide a signal to a destination interconnect line or logic block.
I/Os 12a through 12d can include input/output blocks (IOBs) and high speed transceivers. I/Os 12a through 12d form a perimeter input/output ring having, for example, I/O rows 12a and 12c and I/O columns 12b and 12d. In a conventional FPGA such as Virtex™-II FPGA from Xilinx, Inc., of San Jose, Calif. or Stratix® II device from Altera, Inc., the I/O blocks are located exclusively in the perimeter region of the FPGA, as illustrated by I/Os 12a, 12b, 12c, and 12d of FIG. 1.
The LBs can include configurable logic blocks (CLBs) having look-up-tables, block random access memories (BRAMs), digital signal processing (DSP) blocks, and the like. Typically, the LBs are arranged in partial columns of the same type, for example a partial column of CLBs that may include LBs 11a, 11d, and 11g. The term partial column is used because in FIG. 1 the top and bottom of, for example, the column having LBs 11a, 11d, and 11g, are I/Os 12a and 12c, respectively.
While FPGAs offer much flexibility, they typically have less performance and cost more than an application-specific integrated circuit (“ASIC”). An ASIC is an integrated circuit (“IC”) customized for a particular use, rather than intended for general-purpose use, like an FPGA. Thus, in the past, an FPGA was used for prototyping a design for a particular use and then when the design was verified, the FPGA design was converted to an ASIC for production.
Another variation on this approach, namely of using an FPGA as a prototype and ASICs for production, used the structured ASIC. In a structured ASIC, the logic mask-layers of a device are predefined by the ASIC vendor; in other words, blocks of logic have their transistors already wired together forming gates along with some combination of multiplexers, flip/flops, look up tables, RAMs, and the like. Design customization is achieved by creating custom metal layers that create custom connections between the above-described predefined lower-layer logic elements.
Thus, the Altera Hardcopy™ devices as described in the Hardcopy Series Handbook, Volume 1, pp. 2-1 to 2-7 and 6-1 to 6-10, Copyright 2005 from Altera Inc., allegedly convert a circuit design in an FPGA such as illustrated in FIG. 1 to a structured ASIC design with the same functionality as the FPGA implementation. Basically, the reprogrammable FPGA logic and routing, including the configuration memory and configuration related logic, are stripped from the structured ASIC. Thus, for example, all FPGA programmable and configuration resources may be replaced with direct metal connections, hence there should be a reduction in die size and cost. The structured ASIC also has an I/O perimeter ring, and the I/O features between the FPGA and structured ASIC design are the same. One disadvantage of the structured ASIC is that the DSP block functions are implemented using logic blocks known as HCells (which are also used to implement the CLBs) rather than dedicated DSP blocks. Thus, any advantages due to the customization of the dedicated DSP blocks are lost.
The perimeter I/O ring of the FPGA of FIG. 1 generally means that input/output circuit elements need to be confined to a perimeter region and cannot be in the interior of the IC. The disadvantage of this configuration is that with flip-chip technology, I/O circuit elements can be located in the interior region of the IC. An example is the Virtex-4 columnar architecture FPGA from Xilinx, Inc., which has no perimeter I/O ring, but has I/O circuit elements in one or more columns.
Accordingly, it would be both desirable and useful to provide a columnar application specific circuitry architected design premised on a columnar programmable logic device.